Analogue fault simulation in standard VHDL

摘要

Test development for analogue and mixed-signal circuits has become a bottleneck in the IC development trajectory. A defect-oriented test approach provides an objective test evaluation technique, which alleviates this bottleneck. This test approach, however, makes extensive use of analogue fault simulation, which is very CPU-intensive. It is shown how a standard (digital) VHDL simulation environment can be used to drastically reduce the fault simulation time for complex analogue circuits.