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Modulo multipliers using polynomial rings

机译:使用多项式环的模乘法器

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The performance of many DSP chips depends to a great extent on their multiply-accumulate (MAC) speed. In this direction, the use of residue arithmetic has been proved to enhance the speed of multiplier units. One approach has been to convert all multiplication operations to addition, thereby speeding up the whole operation. This was made possible by defining a logarithmic transform for the integers in a finite field, more specifically in a prime field GF(p). The author extends this approach to the case of polynomial rings (quotient rings), thereby providing more choices for the selection of moduli in RNS multipliers.
机译:许多DSP芯片的性能在​​很大程度上取决于其乘累加(MAC)速度。在这个方向上,使用残差算法已被证明可以提高乘法器单元的速度。一种方法是将所有乘法运算转换为加法运算,从而加快整个运算速度。通过为有限域(更具体地说是质数域GF(p))中的整数定义对数变换,可以实现这一点。作者将这种方法扩展到多项式环(商环)的情况,从而为RNS乘数的模数选择提供了更多选择。

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