As feature sizes move into the deep submicron ranges and powernsupply voltages are reduced, the effect of both device mismatch andninter-die process variations on the performance and reliability ofnanalogue integrated circuits is magnified. The statistical MOS (SMOS)nmodel accounts for both inter-die and intra-die variations. A low powernanalogue CMOS square-law cell, and a new transconductor and multipliernusing this cell as the main building block, are presented in the paper.nThe paper focuses on the robust design of the transconductor andnmultiplier circuits. The circuits operate in the saturation region withnfully balanced input signals. Initial circuit simulation results arengiven. Response surface methodology and design of experiment techniquesnwere used as statistical VLSI design techniques combined with the SMOSnmodel. Device size optimisation and yield enhancement are demonstrated
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