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首页> 外文期刊>IEE proceedings. Part G, Circuits, devices and systems >Optimisation of Reed-Muller PLA implementations
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Optimisation of Reed-Muller PLA implementations

机译:Reed-Muller PLA实施的优化

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Decomposition techniques are utilised for mixed polaritynReed-Muller minimisation, which lead to Reed-Muller programmable logicnarray implementations for Boolean functions. The proposed algorithmnproduces a simplified mixed polarity Reed-Muller format from thenconventional sum-of-products input based on a top-down strategy. Thenoutput format belongs to the most general class of AND/XOR forms, namelynexclusive-OR sum-of-products. This method is further generalised to verynlarge multiple output Boolean functions. The developed decompositionnmethod is implemented in the C language and tested with MCNC and IWLS'93nbenchmarks. Experimental results show that the decomposition method cannproduce much better results than Espresso for many test cases. Thisnefficient method offers compact Reed-Muller programmable logic arraynimplementations with the added advantage of easy testability, inncontrast to the conventional programmable logic array realisations
机译:分解技术被用于混合极性的Reed-Muller最小化,这导致了针对布尔函数的Reed-Muller可编程逻辑阵列实现。所提出的算法基于传统的自顶向下策略,从传统的乘积和输入中产生简化的混合极性Reed-Muller格式。输出格式属于最一般的AND / XOR形式类别,即“异或”乘积之和。将该方法进一步推广到非常大的多个输出布尔函数。所开发的分解方法是用C语言实现的,并已通过MCNC和IWLS'93n基准测试。实验结果表明,在许多测试案例中,分解方法都无法获得比Espresso更好的结果。这种低效率的方法提供了紧凑的Reed-Muller可编程逻辑阵列实现,并具有易于测试的优势,与传统的可编程逻辑阵列实现相反

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