Experimental 128-kbit ferroelectric memory with 1012endurance and 10-year data retention

摘要

An experimental 128-kbit ferroelectric random access memory isnpresented, which has been designed and fabricated with 0.5 Μmnferroelectric storage cell integrated CMOS technology. To achieve stablencell operation, novel design techniques, robust to unstable cellncapacitors, are adopted: open bit-line cell array; up-down pulsed platenread/write-back scheme; complementary data preset reference circuitry;nand non-ferroelectric reference voltage generator. A self-driven cellnplate scheme has also been employed to improve cell array layoutnefficiency. The prototype chip incorporating these circuit schemes showsn70 ns access time and 120 ns cycle time at 3.3 V and 25°C. Thenread/write endurance has been confirmed up to 1012 cycles. Itnhas also been observed that memory cells can retain the data for 10nyears