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Event clock message passing automata: a logical characterization and an emptiness checking algorithm

机译:事件时钟消息传递自动机:逻辑表征和空度检查算法

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摘要

We are interested in modeling behaviors and verifying properties of systems in which time and concurrency play a crucial role. We introduce a model of distributed automata which are equipped with event clocks as in Alur et al. (Theor Comput Sci 211:253-273, 1999), which we call Event Clock Message Passing Automata (ECMPA). To describe the behaviors of such systems we use timed partial orders (modeled as message sequence charts with timing). Our first goal is to extend the classical Buechi-Elgot-Trakhtenbrot equivalence to the timed and distributed setting, by showing an equivalence between ECMPA and a timed extension of monadic second-order (MSO) logic. We obtain such a constructive equivalence in two different ways: (1) by restricting the semantics by bounding the set of timed partial orders: (2) by restricting the timed MSO logic to its existential fragment. We next consider the emptiness problem for ECMPA, which asks if a given ECMPA has some valid timed execution. In general this problem is undecidable and we show that by considering only bounded timed executions, we can obtain decidability. We do this by constructing a timed automaton which accepts all bounded timed executions of the ECMPA and checking emptiness of this timed automaton.
机译:我们对建模行为和验证时间和并发性起关键作用的系统的属性感兴趣。我们介绍了一种分布式自动机模型,该模型配备了与Alur等人一样的事件时钟。 (Theor Comput Sci 211:253-273,1999),我们将其称为事件时钟消息传递自动机(ECMPA)。为了描述此类系统的行为,我们使用定时的部分订单(建模为带有时序的消息序列图)。我们的首要目标是通过显示ECMPA和单调二阶(MSO)逻辑的定时扩展之间的等效性,将经典Buechi-Elgot-Trakhtenbrot等价性扩展到定时和分布式设置。我们以两种不同的方式获得这种构造上的对等:(1)通过限制定时部分顺序的集合来限制语义:(2)通过将定时MSO逻辑限制为其存在的片段。接下来,我们考虑ECMPA的空度问题,该问题询问给定的ECMPA是否具有一些有效的定时执行。总的来说,这个问题是无法确定的,并且我们表明,仅考虑有限的定时执行,就可以得出可确定性。为此,我们构造了一个定时自动机,该自动机接受ECMPA的所有有界定时执行,并检查此定时自动机是否为空。

著录项

  • 来源
    《Formal Methods in System Design》 |2013年第3期|262-300|共39页
  • 作者单位

    Laboratoire de Specification et Verification, ENS Cachan and CNRS, 61;

    Avenue du President Wilson, 94235 Cachan Cedex, France;

    Laboratoire de Specification et Verification, ENS Cachan and CNRS, 61;

    Avenue du President Wilson, 94235 Cachan Cedex, France;

    Laboratoire de Specification et Verification, ENS Cachan and CNRS, 61;

    Avenue du President Wilson, 94235 Cachan Cedex, France;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Message passing automata; Timed automata; MSO logic; Message sequence charts;

    机译:消息传递自动机;定时自动机MSO逻辑;消息序列图;

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