High-Performance Predictable NVM-Based Instruction Memory for Real-Time Embedded Systems

摘要

Worst case execution time and energy consumption are two of the most important design constraints of real-time embedded systems and memory subsystem has a major impact on both of them. Therefore, many recent studies have tried to improve the memory subsystem of embedded systems by using emerging non-volatile memories instead of conventional memories such as SRAM and DRAM. Indeed, the low leakage power dissipation and improved density of emerging non-volatile memories make them prime candidates for replacing the conventional memories. However, accessing these memories imposes performance and energy overhead and using them as the instruction memory could increase the worst case execution time, which would have a negative impact on the system. Furthermore, most previous studies that have tried to address such problems have focused on the data memory and therefore their solutions are not suitable for the instruction memory. In this paper, a new instruction memory architecture for non-volatile memories is proposed which reduces the effective memory access latency by employing memory access interleaving technique. Unlike common instruction access latency improvement techniques such as prefetching which usually increase the worst case execution time of the system, the proposed architecture is predictable and does not increase the worst case execution time of the system. Furthermore, it improves both average case execution time and energy consumption of the system and requires no changes to the application code. The proposed architecture has been evaluated using different applications from MiBench and Malardalen benchmark suites and the results show that compared to previous studies, the proposed architecture can improve the memory energy consumption, the average case execution time, and the worst case execution time of the system by 73, 61, and 27 percent respectively.