Thermal Performance and Reliability Analysis of a Medium-Voltage Three-Phase Inverter Considering the Influence of High dv/dt on Parasitic Filter Elements

摘要

In recent years, the use of silicon carbide (SiC) power semiconductor devices in medium-voltage (MV) applications has been made possible due to the development of high blocking voltage (10-15 kV)-based devices. While the use of these devices brings in a lot of advantages, the semiconductor devices are exposed to high peak stress (of up to 15 kV) and a very high $dv/dt$ (of up to 100 kV/ $mu ext{s}$ ). The high $dv/dt$ across the devices leads to a high $dv/dt$ across other components connected to the system. This makes the effect of the parasitic capacitance across the components to be of paramount importance since an additional current flows through the components and, consequently, through the switching device. This additional current flows during each switching transition and leads to increased switching losses in the device. This article analyzes the effect of these additional losses on the lifetime of the device. The thermal performance of a three-phase inverter power block is provided, and a mission profile (solar irradiance and temperature)-based analysis is carried out to account for the additional junction temperature rise. The rainflow counting method is implemented to identify the mean and amplitude of each thermal cycle. An empirical device lifetime model is used to calculate the number of cycles to failure. Finally, the Palgrem Miner rule is used to quantify the total damage in the device. Comparisons have been carried out on basis of lifetime for both the cases (with and without the influence of parasitic capacitances). This analysis can be helpful in validating the importance of the design of filter inductors in these MV applications.