Robust Clock Network Design Methodology for Ultra-Low Voltage Operations

摘要

Robust design is a critical concern in ultra-low voltage operation due to large sensitivities to process and environmental variations. In particular, clock networks require careful attention to ensure robust distribution of well-defined clock signals to avoid setup and hold time violations. In this paper, we propose two complementary methodologies to design robust and low power clock networks at ultra-low voltage regimes, an un-buffered and buffered approach, which can be chosen from depending on the significance of wire resistance. We confirm the efficacy of the proposed strategies through simulations with test circuits over different supply voltages, technologies, and design sizes. We also perform case studies of low voltage clock network design for a microprocessor and signal processing core. For one case study, we employ the un-buffered methodology, reducing ${+}{hbox{2}} sigma$ skew by ${sim} {hbox{5000}} times$ and ${+}{hbox{2}} sigma$ slew by $sim {hbox{15}}hbox{%}$ without energy overhead, compared to conventional 1-level buffered H-trees. In the other case, a 3-level buffered tree is implemented, with the proposed clock tree reducing ${+}{hbox{2}} sigma$ skew to $sim {hbox{2}} hbox{%}$ of a clock cycle ( ${hbox{0.68}} times$ fanout-of-4 delay) and slew variability $(sigma/ mu)$ to 0.08 at V.