High-Speed AES Encryptor With Efficient Merging Techniques

摘要

This letter presents a new efficient architecture for high-speed advanced encryption standard (AES) encryptor. This technique is implemented using composite field arithmetic byte substitution, where higher efficiency is achieved by merging and location rearrangement of different operations required in the steps of encryption. The proposed architecture is presented with multistage subpipelined architecture that allows having higher efficiency in terms of (throughput/area) than any previous field-programmable gate array (FPGA) implementations.