Toward Error-Correcting Architectures for Cryptographic Circuits Based on Rabii–Keren Codes

摘要

We present an error-correcting architecture for cryptographic circuits that are exposed to maliciously injected faults. The architecture is based on a new class of error-detecting and correcting codes, which combine high rate, large distance, and robustness; that is, they can detect all error patterns injected by a skillful and strategic attacker and automatically correct simpler errors. Correction of errors is superior to detection since it avoids service disruptions and system-level recovery actions. We investigate the architectures using both mathematical analysis and physical fault injection on an field programmable gate array (FPGA) platform, and point out critical divergences between these methods and the need to employ both of them.