The Intimate Memory Interconnect Standard (IMIS) being promoted by the 3D-IC Alliance recently released its official specification for 3D stacking memory chips. Founding members of the Alliance, Tezzaron Semiconductor Corp. and Ziptronix Inc. are already fabricating memory chips using the IMIS port, the first versions of which will be available by the end of 2008. Owing to the low capacitance of the "intimate" connection achieved by stacking a memory die atop a processor die, power consumption is about 24μW/pin compared to 30mW to 40mW per pin for DDR. That low-power in IMIS's 1,000-pin parallel connection between processor and memory limits power consumption to less that 3W, compared to over 30W for conventional interconnects.
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