Compact four bit carry look-ahead CMOS adder in multi-output DCVS logic

摘要

A four-bit carry look-ahead (CLA) CMOS adder based on transistor sharing in a multi-output differential cascode voltage switch (MODCVS) logic is presented. This adder uses a new enhanced CLA unit, which enables the generation of all output carries in one single compact gate structure. Simulation results using HSPICE with CMOS 1.0 /spl mu/m technology designs show that the four-bit adder proposed has 15.7% less transistors, 27.2% less silicon area, /spl sim/14% speed improvement, and a 29.1% reduction in average power consumption compared to a standard DCVS implementation.