4-bit Manchester carry look-ahead adder design using MT-CMOS domino logic

摘要

In this paper, a design of high performance and low power 4-bit Manchester carry look-ahead adder is presented with the help of modified multi-threshold domino logic technique. The introduced MT-MOS transistors decrease the power dissipation of adder circuit by reducing sub threshold leakage current. The FTL dynamic logic is another technique used to increase operating speed of logic circuit, which evaluates the computational blocks partially before the input signals are formalized and then the final evaluation is performed as soon as the input signals arrive. The pre-evaluation logic reduces propagation delay into half. The combination of FTL dynamic logic and MT-CMOS domino logic techniques are yields high fan-out, high switching frequencies since both lower delay and dynamic low power consumption in the arithmetic circuits. A Manchester structure of carry generation employed in carry look-ahead adder minimizes the area of arithmetic circuit by decreasing number of transistors. The simulation results have verified that the proposed techniques are reduced the total power dissipation up to 40%, 55% of propagation delay than the standard dynamic domino CMOS technology.