New Design Method for Tapered Buffer Circuit with TIS (Trench-Isolated Transistor Using Sidewall Gate) and Its Application to High-Density DRAMs

摘要

A new design method has been conceived for a buffer circuit using TIS. In the buffer circuit of a taper type with a fan-out of 3 intended for driving a large load capacitance, a new design procedure is conceived that minimizes the pattern area without sacrificing characteristics such as power consumption. In the new design method, the "pla-nar+TIS" method is employed, in which planar-type transistors are used in the front stage of the buffer circuit while TIS-type transistors are used in the latter stage. This design method is applied to a large-capacity DRAM. Relative to the case in which conventional planar transistors are used, the chip area can be reduced by about 8% without sacrificing characteristics such as power consumption.