1.5-ghz Fpga Family Features Up To 40 Lanes Of 10.3-gbit/s Serdes

摘要

The Speedster family of FPGAs uses picoPIPE acceleration technology that speeds the way data moves through the FPGA fabric. Instead of a global parallel clock, picoPIPEs use simple handshake protocols to efficiently control data flow, resulting in what is said to be significantly improved performance. The 1.5-GHz 65-nm devices have 24,576 to 163,840 LUTs. The fist device in the family is the SPD60 with 47,040 LUTs, twenty 10.3-Gbit/s SerDes, five 5-Gbit/s SerDes, 144 18-Kbit blocks of RAM, and 98 multipliers. The device takes 8 to 10 W, excluding I/O, has four DDR3/DDR2 con- trollers, and comes in a FBBA 1285 or 1892 pack-age.