San Mateo, Calif. - Making good on its promise to offer a unified transaction-level to gate-level verification platform, Cadence Design Systems Inc. has released its Incisive verification platform. The platform and its methodology could cut in half the time it takes to do overall verification of system-on-chip designs, the company said. By most estimates, verification consumes 65 to 75 percent of overall chip development time. But, until now, the design automation industry has addressed the issue with discrete point solutions such as simulators, formal-verification tools, and simulation accelerators and emulators that customers had to tie together to create a verification methodology and flow.
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机译：加利福尼亚州圣马特奥市-Cadence Design Systems Inc.兑现了提供统一交易级别到门级验证平台的承诺，并发布了其Incisive验证平台。该公司表示，该平台及其方法可以将整体验证片上系统设计所需的时间缩短一半。根据大多数估计，验证会消耗整个芯片开发时间的65％至75％。但是，直到现在，设计自动化行业已经通过离散点解决方案解决了该问题，例如，仿真器，形式验证工具以及仿真加速器和仿真器，客户必须将它们结合在一起以创建验证方法和流程。
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