首页>
外国专利>
Unified functional coverage and synthesis flow for formal verification and emulation
Unified functional coverage and synthesis flow for formal verification and emulation
展开▼
机译:用于正式验证和仿真的统一功能覆盖和合成流程
展开▼
页面导航
摘要
著录项
相似文献
摘要
Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.
展开▼