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Altera accelerates Quartus PLD software development environment

机译:Altera加速了Quartus PLD软件开发环境

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摘要

San Mateo, Calif. - Altera Corp. has made the latest version of its Quartus II programmable-logic software development environment faster and easier to use. Version 2.0 improves the LogicLock block-based design capability, adds the FastFit compiler option, boosts network compilation performance and has enhanced debug capability, said Tim Southgate, vice president of software and tools marketing at Altera. The company has added board-level verification tools and support for Altera's MAX7000 PLDs, he said. Southgate said Altera enhanced the algorithms of its LogicLock block-level design methodology so that designers can better control interactive block placement. Users can set performance targets for particular blocks-optimizing I/O timing at the block level, for example-and the tool assists users in achieving optimal floor planning.
机译:加利福尼亚州圣马特奥-Altera公司使Quartus II可编程逻辑软件开发环境的最新版本更加快捷,易于使用。 Altera软件和工具营销副总裁Tim Southgate表示,版本2.0改进了LogicLock基于块的设计能力,增加了FastFit编译器选项,提高了网络编译性能,并增强了调试功能。他说,该公司增加了板级验证工具,并支持Altera的MAX7000 PLD。 Southgate说,Altera增强了LogicLock块级设计方法的算法,以便设计人员可以更好地控制交互式块的放置。用户可以为特定的块设置性能目标,例如,在块级别优化I / O时序-该工具可帮助用户实现最佳的平面规划。

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