Altera Quartus II Software Version 12.1 Now with Enhanced Design Flow

摘要

Altera announced the release of its Quartus II software version 12.1, a design suite for CPLD, FPGA, SoC FPGA and HardCopy ASICs. The latest version strengthens the Quartus II software's high-level design environment by continuing to ease traditional hardware development tasks so users can maximize productivity while benefiting from the broad range of leading-edge capabilities of Altera devices. Quartus II software version 12.1 bolsters its support for high-level design flows with the inclusion of an SDK for OpenCL, and enhancements to both its Qsys system integration tool and DSP Builder model based design environment.