Analog verification IP and the next stage in the evolution of system- on -chip

摘要

Considerable effort is being exerted to improve the quality and success of system-on-chip (SoC) designs. Given the demand for more and more features, lower power requirements, and need for blazing speeds to handle increasing data for video and other hungry applications, it is no surprise that complex SoCs are becoming harder to verify. A comprehensive test and verification strategy is vital; otherwise first-silicon success is unlikely and precious financial resources are wasted. Today's large SoCs can contain tens of millions of gates and require the combination and reuse of intellectual property (IP) blocks for memory, processing and high-speed I/O. Using such blocks can dramatically accelerate development. This cuts the demands on internal resources required to develop an entire design. Engineering teams can focus on the unique value they add to a project while third parties (or other internal design groups) assist with more generic tasks.