New EDA tools ease chip design process

摘要

A year ago, chip engi-neers were fretting about the "timing closure" problem. Even brilliant chip designers were becoming mired in an endless loop in the chip design process. They would design a chip using a high-level synthesis tool, but found that the timing of the chip was off because of delays related to wiring of the chip. They would tweak the design on the abstract level of the synthesis tool, only to find after translation to lower-level tools the design didn't work. So they would change the synthesis design again, in hopes of solving the problem. And so on. It was as if an architect had to design a housing subdivision, without knowing how the roads neighborhood.