随着VLSI技术的迅猛发展与应用需求的不断提高,微处理器中的功耗、时钟偏移等问题越来越严重,异步电路及其设计方法受到广泛关注.异步电路设计缺乏通用商业EDA工具的支持,现有的基于同步EDA工具的异步电路设计方法存在复杂度高等问题.提出了一种新的异步电路设计流程.该流程充分利用现有同步EDA工具,通过采用多路虚拟时钟综合方法对电路进行逻辑综合,以及在后端实现时对异步控制通路进行定量延迟分析和精确延迟匹配,可以得到更加优化的电路.使用该流程在UMC 0.18μm工艺下实现了一款异步微处理器内核,实验结果表明该流程能快速有效地进行大规模异步集成电路的设计实现.%With the rapid development of VLSI technology and the great increase of application requirements, the synchronous circuit with global clock has encountered several crucial problems, such as great clock skew and high power dissipation. Heightened interest in low power consumption and growing concern over clock skew have encouraged the use of asynchronous techniques as a viable approach to future circuit design. But the wide acceptance of asynchronous circuits has been hindered by the lack of commercial EDA tools. Since current design methodologies are difficult for VLSI design and implementation, a novel design flow for asynchronous circuits is presented. By fully using conventional EDA tools, this flow can improve the efficiency and decrease the difficulties of design as well. To obtain optimized circuit structure, multi-virtual clock method is used for logic synthesis. The delay of asynchronous control path is also accurately matched through a quantitative analysis approach. Based on this flow, an asynchronous microprocessor core in UMC 0. 18 μm process is designed and implemented. Experimental results show that this flow can make the design of asynchronous circuits easily and effectively, and the asynchronous circuit style can offer a low power solution for future microprocessor design.
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