机译:关于器件架构,压电场效应晶体管的亚阈值摆幅和功耗(
MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands;
Field effect transistors; Logic gates; Metals; Performance evaluation; Silicon; Strain; CMOS; MOSFET; Piezoelectric effect; piezoelectric effect; steep-subthreshold device; subthermal device;
机译:
机译:B
机译:X射线吸收光谱法研究无序结构(Cu
机译:CxFET:一种新颖的陡峭亚阈值摆幅CMOS,具有隧道注入双极晶体管和MOSFET器件组合
机译:在器件架构上,亚阈值摆幅和压电场效应晶体管(π-FET)的功耗