The SCC BJT: a high-performance bipolar transistor compatible with high-density deep-submicrometer BiCMOS SRAM technologies

摘要

We present the process development and device characterization of the Selectively Compensated Collector (SCC) BJT specifically designed for high-density deep-submicrometer BiCMOS SRAM technologies. This double-poly BJT takes advantage of the self-aligned polysilicon layers of the SRAM bit cell to obtain high performance without adding excessive process complexity. Furthermore, although an NPN device, the SCC BJT is formed in a lightly doped p-well in which the collector is formed with a single 370 keV phosphorus implant to minimize parasitic junction capacitances without the use of trench isolation or recessed oxides. The suitability of this bipolar structure outside of its original FSRAM intent is proven with its potential for bipolar logic and mixed-mode RF applications. ECL delays of 50 ps at 200 /spl mu/A and a CML power-delay product of 4.5 fJ at 1.1 V supply were obtained. A 900 MHz noise figure as low as 0.54 dB at 0.5 mA with an associated gain of 14.7 dB was demonstrated as well as a dual modulus /spl divide/4/5 prescaler operating up to 3.3 GHz for a switch current of 200 /spl mu/A.