The Effects of Double-Epilayer Structure on Threshold Voltage of Ultralow Voltage Trench Power MOSFET Devices

摘要

The effect of double-epilayer structure on threshold voltage (V th) has been investigated for p-channel low-voltage (Vds ) trench power MOSFET devices. By fabricating the device in an intrinsic epilayer grown on the top of a highly doped epilayer, the sensitivity of Vth to the epidoping concentration has been significantly reduced. This reduction is attributed to the fact that in the double-epilayer structure, the compensation effect of epidoping concentration (NA) is minimized. The Vth variation (sigmaVth standard deviation) shows a strong dependence on the intrinsic epilayer thickness (t, in micrometers) as: sigmaVth = 2.4 times 105-7.1, while the device-specific on-resistance (sp-Rdson) is linearly proportional to the intrinsic layer thickness. This intrinsic epilayer can thus be utilized to minimize the boron up-diffusion from both the first epilayer and the substrate and further reduces Vth variation. For the p-channel device with a Vds of 12 V, a 50% lower sigmaVth has been achieved while maintaining at least the same sp-Rdson with the optimized double-epilayer structure which consists of a 4-mum-thick intrinsic layer and a 2.6-mum-thick first doped epilayer (at 4 times 1017 cm-3 or 0.07 Omegamiddotcm). Compared to the single epilayer, the double-epilayer structure also leads to 14% higher device output saturation current and shows the body junction much closer to ideal characteristics (abrupt). This structure enables further reductions of both power consumption and Vth for ultralow voltage power MOSFET