Double-Epilayer Structure for Low Drain Voltage Rating n-Channel Power Trench MOSFET Devices

摘要

Double-epilayer structures were studied for n-channel low-voltage power trench MOSFET devices with drain-to-source voltage $(V_{rm ds})$ of 20 V, and various device performance improvements have been observed. The threshold voltage variation $(sigma_{V_{rm th}})$ can be reduced by increasing the intrinsic epilayer thickness. A 9% effective electron mobility $mu_{n}$ improvement has been observed and is attributed to the reduced background phosphorus scattering. A $Q_{rm gd}$ of 3.1 nC for double-epilayer structure is observed which is about 30% lower than the 4.5 nC for the single-epilayer structure. This improved $Q_{rm gd}$ is due to both an increasing depletion width at the bottom of the trench and the well junction moving toward the trench bottom for the double-epilayer structure. The dependence of $Q_{rm gd}$ on the double-epilayer structure (intrinsic epilayer thickness and the doped epilayer resistivity) is found following the power law $Q_{rm gd}propto aX^{ - b}$, where $a$ and $b$ are double-epilayer structure dependent. Compared to the single-epilayer structure, a double-epilayer structure can handle larger reverse current, suggesting a smaller basis resistance $(R_{{rm bb}^{prime}})$ for the double-epilayer structure. This improvement ranges from 7% to 24% depending on the die pitch. A 20% less temperature dependence of device on-resistance for the double-epilayer structure has also been observed. This enables a large forward curre-nt capability, although the mechanism is not well understood.