首页> 外文期刊>Electron Devices, IEEE Transactions on >High-Performance Slow-Wave Transmission Lines With Optimized Slot-Type Floating Shields
【24h】

High-Performance Slow-Wave Transmission Lines With Optimized Slot-Type Floating Shields

机译:带有优化槽型浮动屏蔽的高性能慢波传输线

获取原文
获取原文并翻译 | 示例

摘要

A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is presented. Periodical slot-type floating shields are inserted beneath the transmission line to provide substrate shielding and to shorten the electromagnetic (EM) propagation wavelength. This is the first study that demonstrates how the wavelength, attenuation loss, and characteristic impedance can be adjusted by changing the strip length (SL), strip spacing (SS), and metal layer position of the slot-type floating shields. Wavelength shortening needs to be achieved with a tradeoff between slow-wave effect and attenuation loss. The slot-type floating shields with different SLs, SSs and metal layer positions are analyzed. It is concluded that minimum SL provides the most optimal result. A design guideline can be established to enable circuit designers to reach the most appropriate slot-type floating shields for optimal circuit performance. Transmission line test structures were fabricated by using 45-nm CMOS process technology. Both measurement and EM waves simulation were performed up to 50 GHz. Transmission lines are frequently used at a length of half- or quarter-wavelength. With a shortened wavelength, a saving in silicon area of more than 67% can be achieved by using optimized slot-type floating shields. Experimental results demonstrated a higher effective relative permittivity value, which is improved by a factor of more than 9, and a better quality factor, which is improved by a factor of more than 6, as compared to conventional transmission lines.
机译:提出了一种采用先进的CMOS技术优化了缝隙型浮动屏蔽的新型慢波传输线。定期的槽型浮动屏蔽层插入传输线下方,以提供基板屏蔽并缩短电磁(EM)传播波长。这是第一项研究,展示了如何通过改变狭缝式浮动屏蔽的条带长度(SL),条带间距(SS)和金属层位置来调节波长,衰减损耗和特性阻抗。需要通过在慢波效应和衰减损耗之间进行权衡来实现波长缩短。分析了具有不同SL,SS和金属层位置的槽型浮动屏蔽。结论是最小SL提供了最佳结果。可以建立设计指南,使电路设计人员能够接触最合适的槽型浮动屏蔽,以实现最佳的电路性能。传输线测试结构是使用45纳米CMOS工艺技术制造的。测量和电磁波仿真均在高达50 GHz的频率下进行。传输线的波长通常为一半或四分之一波长。在缩短波长的情况下,通过使用优化的缝隙型浮动屏蔽可以节省超过67%的硅面积。实验结果表明,与传统的传输线相比,更高的有效相对介电常数值可以提高9倍以上,而更好的品质因数可以提高6倍以上。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号