Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications

摘要

We have experimentally studied the scaling behavior of sub-100-nm InAs high-electron mobility transistors (HEMTs) on InP substrate from the logic operation point of view. These devices have been designed for scalability and combine a thin InAlAs barrier and a thin channel containing a pure InAs subchannel. InAs HEMTs with gate length down to 40 nm exhibit excellent logic figures of merit, such as $I_{scriptstyle{ rm ON}}/I_{scriptstyle{rm OFF}} = hbox{9} times hbox{10}^{4}$, $hbox{drain-induced-barrier lowering} = hbox{80} hbox{mV/V}$, ${S} = hbox{70} hbox{mV/dec}$, and an estimated logic gate delay of 0.6 ps at $V_{DS} = hbox{0.5} hbox{V}$. In addition, we have obtained excellent high-frequency operation with $L_{g} = hbox{40} hbox{nm}$ , such as $f_{T} = hbox{491} hbox{GHz}$ and $f_{max} = hbox{402} hbox{GHz}$ at $V_{DS} = hbox{0.5} hbox{V}$. In spite of the narrow bandgap of InAs subchannel, under the studied conditions, our devices are shown not to suffer from excessive band-to-band tunneling. When benchmarked against state-of-the-art Si devices, 40-nm InAs HEMTs exhibit $I_{scriptstyle{rm ON}} = hbox{0.6} hbox{A}/muhbox{m}$ at $I_{rm Leak} = hbox{200} hbox{nA}/muhbox{m}$. This is about two times higher $I_{script-n-nstyle{rm ON}}$ than state-of-the-art high-performance 65-nm nMOSFET with comparable physical gate length and $I_{rm Leak}$.