Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic

摘要

Microelectromechanical relays have recently been proposed for ultra-low-power digital logic because their nearly ideal switching behavior can potentially enable reductions in supply voltage $(V_{rm dd})$ and, hence, energy per operation beyond the limits of MOSFETs. Using a calibrated analytical model, a sensitivity-based energy–delay optimization approach is developed in order to establish simple relay design guidelines. It is found that, at the optimal design point, every 2 $times$ energy increase can be traded off for a $sim!!hbox{1.5}times$ reduction in relay delay. A contact-gap-to-actuation-gap thickness ratio of 0.7–0.8 is shown to result in the most energy-efficient relay operation, implying that pull-in operation is preferred for an energy-efficient relay design. Based on the analytical model and design guidelines, a scaling theory for relays is presented. A scaled relay technology is projected to provide $>hbox{10}times$ energy savings over an equivalent MOSFET technology, for circuits operating at clock frequencies up to $ sim$100 MHz.