Investigation of Hysteresis Phenomenon in Floating-Gate NAND Flash Memory Cells

摘要

The origin of hysteresis phenomenon in floating-gate (FG) NAND flash memory cells in cell strings was identified. To analyze the hysteresis phenomenon in FG NAND flash memory strings, pulsed – and fast transient bitline current () measurements were used in this study. It was found that the hysteresis phenomenon is originated by traps in the bottom oxide of the oxideitride/oxide interpoly dielectric. When the control-gate voltage () of a selected cell in the erased state is 5 V, the electrons in the FG are captured in the traps, because the trap energy level () is lower than the Fermi energy level () of the FG (), which leads to the increase in . When the of the selected cell is , trapped electrons are emitted to the FG, because the is higher than the of the FG (), which leads to the decrease in .