Dual-Gate JFET Modeling I: Generalization to Include MOS Gates and Efficient Method to Calculate Drain–Source Saturation Voltage

摘要

This paper presents an accurate and computationally efficient method to calculate the drain–source saturation voltage of dual-gate (i.e., four-terminal) junction field-effect transistors. The method accounts for velocity saturation and for channel thickness modulation by any combination of MOS or p-n junction gates. In three iterations, it achieves an error of less than 2%. Our algorithm converges significantly faster than the direct application of the Newton–Raphson method because of careful selection of an initial value and the leverage of the convex and concave nature of the curves whose intersection defines . The method is applied to both the exact model for and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation.