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Novel Approach for the Reduction of Leakage Current Characteristics of 20 nm DRAM Capacitors With ZrO–Based High-k Dielectrics

机译:基于ZrO的高k电介质降低20 nm DRAM电容器漏电流特性的新方法

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摘要

In order to produce a dynamic random access memory (DRAM) of 20 nm or less, the most important concern regarding development is to reduce the leakage current degradation of the capacitor using high-k dielectrics. We studied the effect of defect sources present after the formation of the capacitor and measured the leakage current characteristics of the capacitor using the dielectric breakdown degradation test, a test used in mass production. From these results, we confirmed that the leakage current degradation was completely eliminated by removing external impurities of boron and hydrogen without any change in the structure or materials of the capacitor. For further DRAM scaling, we propose a method of reducing leakage current degradation of the capacitor.
机译:为了生产20 nm或更小的动态随机存取存储器(DRAM),与开发相关的最重要的考虑是减少使用高k电介质的电容器的漏电流劣化。我们研究了电容器形成后存在的缺陷源的影响,并使用电介质击穿退化测试(一种用于批量生产的测试)测量了电容器的漏电流特性。从这些结果,我们确认了通过除去硼和氢的外部杂质而完全消除了漏电流的劣化,而电容器的结构或材料没有任何变化。为了进一步进行DRAM缩放,我们提出了一种减少电容器泄漏电流退化的方法。

著录项

  • 来源
    《IEEE Electron Device Letters》 |2017年第11期|1524-1527|共4页
  • 作者单位

    DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;

    DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;

    DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;

    DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;

    DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;

    DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;

    College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Leakage currents; Capacitors; Dielectrics; Degradation; Random access memory;

    机译:漏电流电容器介电性能退化随机存取存储器;

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