机译:基于ZrO的高k电介质降低20 nm DRAM电容器漏电流特性的新方法
DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;
DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;
DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;
DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;
DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;
DRAM Process Architecture Team, Samsung Electronics Co., Hwasung, South Korea;
College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea;
Leakage currents; Capacitors; Dielectrics; Degradation; Random access memory;
机译:电容器形成后热预算对下一代动态随机存取存储器电容器ZrO2高k电介质漏电流特性的影响
机译:Y掺杂ZrO 2 sub>和低漏电流的Ge MOSFET超薄EOT(0.67 nm)高k电介质
机译:使用Y掺杂的ZrO 2 Sub>具有记录低漏电流的GE MOSFET上的超薄EOT(0.67nm)高k电介质
机译:开发新的锡/ ZrO {sub} 2 / al {sub} 2o {sub} 3 / zro {sub} 2 / tin电容器可扩展到45nm代置DRAM替换基于HFO {sub} 2的电介质
机译:DRAM电容器的电和介电特性。
机译:四(二甲基氨基)锆和臭氧原子层沉积生长的高k ZrO2薄膜的结构和介电性能
机译:用于20 nm以下DRAM技术节点的低泄漏基于ZrO2的电容器