VERIFICATION TAKES as much as 70% of an ASIC's development time and resources. With growing ASIC complexity, verification problems are growing exponentially. Given the high cost of ASIC mask sets, the financial impact of a silicon respin is substantial. As a result, ASIC designers tend to prototype their designs on FPGA platforms before tape-out. FPGA prototyping can offer substantial performance gains, resulting in a 1000- to 100,000-times throughput improvement over HDL simulation. The recent advancements in FPGA densities have enabled designers to build FPGA prototypes of large ASICs without worrying about FPGA logic-resource usage and changes that may result in higher gate counts. Today's FPGAs with integrated high-performance microprocessors have millions of gates, and compete directly with low-range to midrange ASICs. Although these complex systems offer many advantages, they also require significant verification with superior debugging capabilities.
展开▼
