Design-planning guidelines prevent chip surprises

摘要

Design-planning strategies become com-mon sense once you grasp the complex tradeoffs they involve. One way to achieve that intuitive grasp is to understand some rules of thumb for good design planning. These practical considerations come from the day-to-day experience of dealing with flporplanning and power-planning issues. Getting good at design planning can help you prevent time-consuming iterations and chip respins. Design planning has become crucial for big chips with hierarchical design flows because such chips are more likely to have long interblock paths whose delays make timing closure impossible. For any complex chip, you need power planning to prevent problems due to IR drop and electromigration. The rules of thumb range from basic to advanced, and they can benefit both a COT (customer-owned-tooling) design flow and an ASIC flow, in which the ASIC vendor handles the actual back-end design. Figure 1 shows a typical design-planning flow.