Selecting the correct process geometry and options

摘要

Most of the custom chips today, including ASICs, ASSPs (application-specific standard products), and special-purpose custom chips, have function blocks that do not require leading-edge processes. This situation has introduced the task of selecting which process node is the most appropriate for the design opportunity. The traditional metric for process selection is the speed requirement for the logic and the associated pin-to-pin clock rate. These criteria determinernthe minimum device geometry, the junction profiles, the number of layers of interconnect--which in turn determines the areal density of gates-and the type of substrate material. Most of the digital-only designs with fewer than 100 million gates use these criteria, and they work well.