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Using enhanced triggering to verify and debug complex designs

机译:使用增强的触发来验证和调试复杂的设计

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摘要

Analyzing systems that always fail is not difficult. The more difficult challenge is to debug systems such as a clock that intermittently outputs an incorrect duty cycle or a rise time that occasionally fails specifications. Adding to the challenge are complex high-speed serial buses that use CDR (clock-data-recovery) techniques for data transmission or specialized 8b/10b encoding schemes. A further level of complexity is the trend toward multilane serial configurations.As waveforms become more complex, the basic edge trigger has become too limited as the sole means of initiating an acquisition. Edge triggering simply doesn't give the oscilloscope enough useful information about when to start capturing a waveform, making it difficult to find infrequent errors. Fortunately, trigger capabilities have evolved to keep pace with the increase in signal complexity.
机译:分析总是失败的系统并不困难。更为困难的挑战是调试诸如时钟之类的系统,该系统会间歇性地输出错误的占空比或上升时间(有时会导致规格不合格)。使用CDR(时钟数据恢复)技术进行数据传输或专用的8b / 10b编码方案的复杂高速串行总线使挑战更加复杂。复杂性的进一步发展是多通道串行配置的趋势。随着波形变得越来越复杂,基本的边沿触发已被限制为启动采集的唯一手段。边沿触发根本无法为示波器提供足够的有用信息来说明何时开始捕获波形,因此很难发现不常见的错误。幸运的是,触发功能已经发展,可以跟上信号复杂性的增长步伐。

著录项

  • 来源
    《Electrical Design News》 |2011年第1期|p.36-39|共4页
  • 作者

    JIT LIM;

  • 作者单位

    TEKTRONIX INC;

  • 收录信息 美国《科学引文索引》(SCI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

  • 入库时间 2022-08-18 00:29:58

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