From AHPL to VHDL: a course in hardware description languages

摘要

As the size and complexity of digital systems increase, more CAD tools are introduced in the hardware design process; a recent addition to this process is the use of hardware description languages (HDLs). Historically, HDL-based design courses have been taught mostly at the graduate level. Undergraduate courses have mainly emphasized the principles of digital systems design, at both the logic and architectural levels. The laboratory component of these courses often introduces the students to graphical design capture tools and their associated simulators. However, within the past few years industry has been moving away from graphical design captures and is more openly adopting HDL-based design methodologies. Based on these industry shifts, one can easily conclude that HDLs are becoming an integral part of the design automation environments; this in turn requires the updating of the curricula, either by incorporating new courses or by updating existing ones. Specifically, courses that introduce undergraduates to HDLs in general and a standard language such as VHDL or Verilog are becoming essential in preparing future engineers. This paper discusses an HDL-based design course offered at Northern Arizona University (NAU). The course is used as a vehicle to introduce NAU students to the underlying concepts behind modeling, simulating, and verifying-digital systems design using hardware description languages.