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Power Electronics Design Laboratory Exercise for Final-Year M.Sc. Students

机译:硕士最后一年的电力电子设计实验室练习学生们

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This paper presents experiences and results from a project task in power electronics for students at Chalmers University of Technology, GÖteborg, Sweden, based on a flyback test board. The board is used in the course Power Electronic Devices and Applications. In the project task, the students design snubber circuits, improve the control of the output voltage, improve the gate drive of the main MOSFET transistor and study the influence of stray inductance. The project goals (the circuit improvements) are given, but the procedure for solving the problems and obtaining the results is not specified. Instead the students have to make their own specification in order to reach the goals. “Tools” that are given to the students are the hardware, measurement equipment, an example of the circuit in the circuit simulation software PSpice, and lastly lectures covering the material needed in order to attain the project goals. The project design builds on the ideas from the CDIO (Conceive, Design, Implement, Operate) initiative, where students are encouraged to consider the complete process structure. The result found was a substantial engagement by the students, who had both positive and negative reactions. The negative reactions were mainly that the project specification was too vague, in other words in the (C=Conceive)-phase of the CDIO structure. Further, the teachers observed increased learning, which also was noticeable for the students performing their M.Sc. thesis within the power electronics design area. Finally, it was found that a final written exam is definitely still needed to assess students adequately in the course.
机译:本文基于反激测试板,向瑞典哥德堡查尔姆斯理工大学的学生介绍了电力电子项目任务的经验和结果。该板用于“电力电子设备和应用”课程。在项目任务中,学生将设计缓冲电路,改善输出电压的控制,改善主MOSFET晶体管的栅极驱动,并研究杂散电感的影响。给出了项目目标(电路改进),但未指定解决问题和获得结果的步骤。相反,学生必须制定自己的规范才能达到目标。提供给学生的“工具”是硬件,测量设备,电路仿真软件PSpice中的电路示例,最后讲授了实现项目目标所需的材料。项目设计基于CDIO(构思,设计,实施,操作)倡议的思想,鼓励学生考虑完整的过程结构。发现的结果是学生积极参与,产生了积极和消极的反应。负面反应主要是项目说明过于模糊,换句话说就是CDIO结构的(C = Conceive)阶段。此外,教师观察到学习的增加,这对于表演其硕士课程的学生也很明显。电力电子设计领域的论文。最后,发现肯定仍需要期末笔试来对课程中的学生进行充分评估。

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