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Knowledge of clocking aids ASIC-emulator choice

机译:时钟知识有助于ASIC仿真器选择

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Originally, ASIC emulators used simple clocking-the target system supplied it. However, as custom-processor-based emulators emerged and manufacturers added multiplexed I/O capabilities to increase the efficiency of FPGA-based machines, the methods of internal and external clocking for emulation systems became quite complex and confusing, Learning how to categorize the various clock methods and how the methods work can clear up some of this mystery. Once you know the pros and cons of each method, you can make a more informed decision when choosing an emulator. Emulators divide into three categories: those that exhibit pure event behavior, those that exhibit pure cycle behavior, and hybrids. Each category handles various target-system clock situations, single-clock-domain environments, and environments that contains multiple, asynchronous clocks. By understanding how the categories manage these conditions, you can determine each method's advantages and disadvantages.
机译:最初,ASIC仿真器使用简单的时钟-目标系统为其提供时钟。但是,随着基于定制处理器的仿真器的出现以及制造商增加了多路I / O功能以提高基于FPGA的机器的效率,仿真系统的内部和外部时钟方法变得相当复杂和令人困惑,学习如何对各种不同的系统进行分类时钟方法以及这些方法的工作原理可以消除一些神秘感。一旦了解了每种方法的优缺点,就可以在选择仿真器时做出更明智的决定。仿真器分为三类:展示纯事件行为的仿真器,展示纯循环行为的仿真器和混合仿真器。每个类别都处理各种目标系统时钟情况,单时钟域环境以及包含多个异步时钟的环境。通过了解类别如何管理这些条件,可以确定每种方法的优缺点。

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