FPGA implementation of 10 G Ethernet-based DAQ systems for pixel detectors

摘要

Background High Energy Photon Source-Test Facility is a project to study and verify the feasibility of the key technologies which will be applied to that of High Energy Photon Source (HEPS). The pixel array detector is one of the most important components of synchrotron radiation detection. Purpose In order to meet the requirements of the X-ray detection of HEPS, it was asked to independently develop a pixel array detector prototype with an effective detection area larger than 8x8cm2, a spatial resolution better than 200 mu m, a detectable energy range from 8 to 20 keV, and a frame rate higher than 1 kHz. The readout electronics system using the field-programmable gate array (FPGA) as its core of the digital logic makes the basic functions of the detector prototype feasibility by implementing all the configuration and data readout of the BPIX which is the dedicated pixel readout chip designed for Chinese next generation of synchrotron light source and working in the single-photon counting mode. Considering the large amount of data generated by pixel detectors and the demand for real-time data acquisition at higher frame rates, a firmware based on the TCP/IP protocol was developed in FPGA. Methods The implementation of 1 G/10 G Ethernet hub firmware provides a method of processing multi-ports Gigabit data and improving bandwidth. The key idea is the conversion of the GMII/XGMII bus in 1 G/10 G Ethernet protocol and the Arbitrator module applying Round-Robin algorithms. Results and conclusion The firmware converts and gathers TCP/IP frames from Gigabit network to 10-Gigabit network successfully. Through measurement, the bandwidth of the hub can reach 8.57 Gbps. A pixel detector integrated with 1 G/10 G Ethernet hub completes the readout of large flux data on 1.5 mega pixels detector at 1.2 kHz frame rate.