Design of Multilayer Fractal Capacitor in 0.18μm RF CMOS process

摘要

In this Paper, Multilayer capacitor is proposed based on chord fractal space filling curvein0.18μm RF CMOS process. The Proposed capacitor uses the both vertical and lateral electric fields. The capacitance density increases as number of layers increases with proper contact of vias in CMOS process. The design strategy is proposed for an on-chip area of 100 × 100 μm2. The Proposed capacitor achieves a 50 % higher capacitance value than the standard chord capacitors of similar on-chip area with a reasonable Q factor and Self resonant frequency for RF applications.