In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting test vectors only between the less correlative test patterns. This paper presents the RC-ATPG with an external circuit. The external circuit consists of XOR gates, full adders, and multiplexers. First the total number of transitions between the consecutive test patterns is determined. If it is more, then the external circuit generates and inserts test vectors in between the two test patterns. Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation. The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG. Experimental results based on ISCAS’85 and ISCAS’89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic.
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