A Design of Digital Stopwatch Circuit with Chip Implementation

摘要

This paper outlines the design, simulation, and testing of a stopwatch circuit using Tanner S-Edit and L-Edit design environment. The configuration of this chip includes button synchronizer, main sequencer unit and a seven-segment decoder. Schematic and layout of the chip was developed using Tanner design suite. After fabrication, test vectors were generated, and applied in simulation and on the physical chip. Improvements were made to create a golden design version of the chip that passed testing. An attempt was made to implement this design, including the missing modules, onto a Custom Programmable Logic Device (CPLD).