Design of Baugh–Wooley multiplier in quantum‑dot cellular automata using a novel 1‑bit full adder with power dissipation analysis

摘要

Complementary metal oxide semiconductor (CMOS) is a low-power technology typically used in the efficient implementationof digital circuits. However, at nanodimensions, CMOS has problems due to its short channel effects andsubthreshold leakage currents. These drawbacks can be overcome with quantum-dot cellular automata (QCA) which isone of the fastest nanotechnologies operated at THz rate. Thus, all digital circuits can now be implemented by QCA at therequired nanoscale. This paper proposes a novel, energy-efficient and area-optimized 1-bit full adder design using QCAwhich provides efficient clocking, reduced cell count and reduced energy dissipation. The proposed design utilizes only26 quantum cells in 0.02 μm~2 area and has a reduction of 8% in number of cells, 75% in delay and 4% in energy dissipationat 1 K compared to the existing works. This innovative full adder design is used to implement a 4 × 4 Baugh–Wooleymultiplier. The simulation results of the multiplier observed on QCADesigner 2.0.3 tool validate that the Baugh–Wooleymultiplier designed with the novel 1-bit full adder yields better performance in terms of 9% reduction in area, 17.4%reduction in quantum cells used and reduced power dissipation of 2.44nW.