An Efficient Low Complexity Low Latency Architecture for Matching of Data Encoded With Error Correcting Code Using a Cache Memory

摘要

An efficient architecture is introduced for the matching of data encoded with error correcting code using a cache memory is presented in brief. Using cache memory it reduces latency and complexity to an fine level. And this architecture further reduces the dynamic power without affecting the time. For the comparison of data, hamming distance along used to check whether the data match the data kept in main memory. Instead of butterfly formed weight accumulator(previous work) here no other mechanism is presented for calculating hamming distance.