This paper bring out a 32X32 bit reversible Vedic multiplier using "Urdhva Tiryakabhayam" sutra meaning vertical and crosswise, is designed using reversible logic gates, which is the first of its kind. Also in this paper we propose a new reversible unsigned division circuit. This circuit is designed using reversible components like reversible parallel adder, reversible left-shift register, reversible multiplexer, reversible n-bit register with parallel load line. The reversible vedic multiplier and reversible divider modules have been written in Verilog HDL and then synthesized and simulated using Xilinx ISE 9.2i. This reversible vedic multiplier results shows less delay and less power consumption by comparing with array multiplier.
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机译：本文使用可逆逻辑门设计了使用“ Urdhva Tiryakabhayam”经文的32X32位可逆吠陀乘法器，其含义是纵向和横向。同样在本文中，我们提出了一种新的可逆无符号除法电路。该电路是使用可逆组件设计的，例如可逆并行加法器，可逆左移寄存器，可逆多路复用器，具有并行负载线的可逆n位寄存器。可逆吠陀乘法器和可逆除法器模块已用Verilog HDL编写，然后使用Xilinx ISE 9.2i进行了合成和仿真。与阵列乘法器相比，这种可逆的吠陀乘法器结果显示出更少的延迟和更低的功耗。
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