Modeling and Estimation of Total Leakage Current in Nano-scaled 7T SRAM Cell Considering the Effect of Parameter Variation

摘要

In this paper we have modeled and estimated the gate leakage , the sub threshold, and the total leakage in nano scaled 7T SRAM cell by considering variation in process parameters like transistor width, oxide thickness. We have verified the results using an NMOS device of 45nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage. The identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This research evaluates various leakage components with parameter variation effects in 7T SRAM cell at the 45nm technology node using Cadence tool with 0.7 supply voltage . The primary contribution of this work is to estimate and modeled gate leakage, sub threshold leakage and total leakage of 7T SRAM cell by considering the effects of parameter variation. Keywords: