Design of Enhanced Power Gating Technique to Reduce Leakage Power and Ground Bounce Noise for CMOS Applications

摘要

In CMO S integrated circuit design there is a trade-off between static power consumption and technology scaling. Leakage power accounts for an increasingly larger portion of total power consumption in deep submicron technologies. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using dual stack approach without being penalized in area requirement and circuit performance