The digital phase locked loop is a circuit that used frequently in modern integrated circuit design. A digital phase-locked loop (DPLL) is designed using 0.18 um CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz¨C1 GHz. DPLL perform the fuction of generating a clock signal, which is locked or synchronized with the incoming signal. It consist of single charge pump (CP), low pass filter (LPF) and voltage controlled oscillator (VCO). DPLL circuit components as well as implementation using Tanner design tools are presented. Spectra simulations were also performed and demonstrated a significant improvement in the lock time of the DPLL
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机译：数字锁相环是现代集成电路设计中经常使用的电路。使用0.18 um CMOS工艺和3.3 V电源设计了数字锁相环（DPLL）。它的工作频率范围为200 MHz–C1 GHz。 DPLL执行生成时钟信号的功能，该时钟信号将与输入信号锁定或同步。它由单电荷泵（CP），低通滤波器（LPF）和压控振荡器（VCO）组成。本文介绍了DPLL电路组件以及使用Tanner设计工具的实现。还进行了光谱仿真，并证明了DPLL锁定时间的显着改善
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